1. Field of the Invention
The present invention relates to a digital audio processor, and more particularly, to a digital audio processor using a 5V tolerant input/output circuit. Although the present invention is suitable for a wide-scope of applications, it is particularly suitable for effectively coping with a high voltage applied to semiconductor devices.
2. Discussion of the Related Art
As shown in FIG. 1, a conventional digital audio processor includes a pair of inverters 1, 2 respectively inverting an enable signal EN and a data signal D, a NOR gate 3 NORing output signals from the inverters 1, 2, a NAND gate 4 NANDing the output signal from the inverter 2 and the enable signal EN, a pair of inverters 5, 6 respectively inverting the output signals from the NOR gate 3 and the NAND gate 4 and outputting a PMOS gate signal PG and an NMOS gate signal NG, a PMOS transistor 7 and an NMOS transistor 8 serially connected with each other between a supply voltage Vcc and a ground voltage Vss and respectively receiving gate signals PG and NG from the respective inverters 5, 6, and a pair of inverters 9, 10 connected in series to an output node D.sub.IN and a pad PAD and sequentially inverting a signal applied to the pad PAD.
FIG. 2 is a cross-sectional view illustrating the PMOS transistor 7 and the NMOS transistor 8 in the conventional input/output circuit shown in FIG. 1.
The operation of the conventional input/output circuit as aforementioned will be now described with reference to the accompanying drawings.
Initially, when the enable signal EN remaining at a high level so that it becomes an output mode, the enable signal EN is inverted in the inverter 1. Simultaneously, the enable signal EN is also applied to an input terminal of the NAND gate 4. When a high level data signal D is applied, the data signal D is inverted in the inverter 2 and applied to the respective input terminals of the NOR gate 3 and the NAND gate 4.
The NOR gate 3 and the NAND gate 4 respectively output high level signals, and the inverters 5, 6 invert the high level signals and output signals to the PMOS gate signal PG of the PMOS transistor 7 and the NMOS gate signal NG of the NMOS transistor 8. Accordingly, the PMOS transistor 7 becomes turned on and the NMOS transistor 8 becomes turned off. As a result, the pad PAD is turned to a high level identical to the data signal D.
Next, when the enable signal EN and the data signal D are at a high level and a low level, respectively, the output signals from the NOR gate 3 and the NAND gate 4 become a low level. Then, both the PMOS gate signal PG of the PMOS transistor 7 and the NMOS gate signal NG become a low level. Therefore, the PMOS transistor 7 becomes turned off and the NMOS transistor 8 becomes turned on, so that the PAD becomes a low level identical to the data signal D.
On the other hand, when the enable signal EN remains at a low level so that it becomes an input mode, the enable signal EN is applied to an input terminal of the NAND gate 4 and at the same time inverted in the inverter 1.
The NOR gate 3 then outputs a low level signal irrespective of the level of the data signal D and the NAND gate 4 outputs a high level signal irrespective of the level of the data signal D. Thus, both the PMOS transistor 7 and the NMOS transistor 8 become turned off.
At this time, when a high level signal is applied to the pad PAD, an input signal D.sub.IN outputted from the inverters 9, 10 becomes a value identical to the pad PAD.
As shown in FIG. 2, the pad PAD is connected to both a P+ active serving as a drain of the PMOS transistor 7 and an N+ active serving as a drain of the NMOS transistor 8. For example, when the supply voltage Vcc is 3.3V, a source region P+ of the PMOS transistor 7 and an N-Well of the substrate also become 3.3V.
When the pad PAD is applied at 5V, the drain region P+ of the PMOS transistor 7 becomes 5V and the drain region P+ forms an N-Well in the substrate and a PN diode of the PMOS transistor 7 and is turned on in a forward direction. Accordingly, in accordance with the turned-on PN diode, the in the substrate N-Well in the substrate of the PMOS transistor 7 becomes 5V and is connected to the supply voltage Vcc through an N-Well Plug. As a result, since the input of the 5V PAD and the supply voltage Vcc at 3.3V become short-circuited, an error occurs in the operation of the MOS transistors. In other words, when the voltage at the pad PAD is higher than that of the supply voltage Vcc, the operation of MOS transistors become problematic.